Technical Field
The present invention relates to semiconductor devices and processing, and more particularly to a multi-tiered via structure and methods for forming the same.
Description of the Related Art
With the use of multiple substrate materials for semiconducting processing, devices may be disposed at different heights across a chip. In one example, complementary metal oxide semiconductor (CMOS) devices may have NMOS devices and PMOS devices formed with different substrate materials for the bodies of the devices. In one application, a step height exists between a III-V material employed for NMOS devices (higher devices) and a silicon material employed for PMOS devices (lower devices). In some instances the step may be significant, e.g., 40 nm in a 22 nm technology.
The step height can result in difficulty forming contact via holes. Contact via holes typically include a cone or wedge shape, being thicker at the top and thinner at the bottom. To provide proper contacts for an interface to lower devices, the wedge size of the contact via becomes too large at the top to fit between higher devices.